(a) Field of the invention
The present invention pertains to an amplifier having an input stage differential amplifying circuit with a large voltage amplification factor.
(b) Description of the prior art
A typical example of circuit diagram of a known amplifier of this type is shown in FIG. 1, which comprises: an input stage amplifying circuit having a pair of field effect transistors (hereinafter to be referred to briefly as FET or FET'S) 1 and 2, a potentiometer 3 assigned for offset adjustment and having an overall resistance value Rs, a constant current source 4, and a load resistor 5 having a resistance value Rl/2 for the FET 1 and another load resistor 6 having a resistance value Rl/2 for the FET 2; and a next stage differential amplifying circuit having a pair of transistors 8 and 9, a resistor 7 inserted in common in the respective emitter circuits of these paired transistors 8 and 9, and a load resistor 10 for the transistor 9. If the transconductance of these FET's is designated as g.sub.m, the voltage gain Av of the input stage amplifying circuit is expressed by: ##EQU1## Accordingly, in order to enhance the voltage gain Av in the amplifier shown in FIG. 1, there may be considered various ways such as: (a) increasing the resistance value Rl/2 of the respective load resistors 5 and 6, (b) increasing the transconductance g.sub.m of the FET's (it is considered in general that it is only necessary to increase the drain currents of FET's in order to increase the transconductance g.sub.m of these FET's), and (c) minimizing the value Rs of the potentiometer. It should be noted, however, that in case the resistance value Rl/2 of the load resistors 5 and 6 is increased to enhance the voltage gain of the amplifier, it will be necessitated to minimize the drain currents of the respective FET's 1 and 2 in association with the voltage level of the power supply. Also, in case the drain currents I.sub.d of the FET's 1 and 2 are increased, for the same purpose stated above, it will become necessary to minimize the resistance value Rl/2 of the load resistors 5 and 6. Furthermore, the value Rs of the variable resistor need to have a value of a certain extent, i.e. several tens of ohms, to expect balanced differential operation of the amplifier. For these reasons, in the conventional amplifiers of the type whose input stage is constructed by a differential amplifying circuit using, especially, FET's, it has been difficult to expect stabilized operation at high voltage gain.
On the other hand, as a circuit for obtaining a high voltage gain, there is known the so-called differential three-stage amplifying circuit. This prior art amplifying circuit, however, has the inconveniences and difficulties such as the difficulty in performing compensation of phase, lack of stable operation and complexity of circuit arrangement.